1. Field of the Invention
The invention relates to a gate array consisting of unit cells on a semiconductor substrate, and in particular to wiring between unit cells.
2. Description of the Related Art
In general in gate arrays, unit cells with P channel MOS transistors (referred to as “PMOS” below) and N channel MOS transistors (referred to as “NMOS” below), and gate wiring for the PMOS and NMOS, are placed in specific positions on a semiconductor substrate. By carrying out wiring between the unit cells, desired logic circuits can be configured.
FIGS. 2A to 2C are block diagrams for explanation of one example of a gate array using unit cells, wherein FIG. 2A is a plan view, FIG. 2B is a cross sectional view taken on line X-X in FIG. 2A, and FIG. 2C is a cross sectional view taken on line Y-Y in FIG. 2A.
This unit cell 10 is formed on a p-type semiconductor substrate 1, and two PMOSs 12a, 12b are formed aligned in an n-well 11 at the top side of the plan view. At the lower side of the plan view there are two NMOSs 13a, 13b formed aligned on the p-type semiconductor substrate 1. The gates of PMOS12a and NMOS13a are connected with gate wiring 14a of polysilicon, and a gate terminal portion 15a with a comparatively wide area is formed in the middle of gate wiring 14a. In the same way, the gates of PMOS12b and NMOS13b are connected with gate wiring 14b of polysilicon, and two gate terminal portions 15b1 and 15b2 with a comparatively wide area are formed between the ends of gate wiring 14b. Further, outside of PMOS12a, 12b (the top side of FIG. 2A) there is an n+ region 16 formed for use as a source potential region, and on the outside of NMOS13a, 13b (the bottom side of FIG. 2B) there is a p+ region 17 formed for use as a ground potential region GND. A gate array base is constructed with unit cells 10 like this arranged with the same orientation vertically and laterally across a semiconductor substrate 1.
The surface of the gate array base is covered with a first insulating layer 20, and on the surface of this first insulating layer 20 is formed a first metal wiring layer 30, and the gate array base and the first metal wiring layer 30 are placed in electrical contact through contactors 31. It is not shown in the Figures, but there is a second insulating layer on the surface of the first metal wiring layer 30, and on the surface of this second insulating layer is formed a second metal wiring layer 50, and the first metal wiring layer and the second metal wiring layer are electrically connected via through holes. Further, depending on the scale of the circuit, a third metal wiring layer and a fourth metal wiring layer and the like can be used.
FIGS. 3A, 3B are block diagrams for explanation of one example of a conventional gate array using unit cells of FIG. 2, wherein FIG. 3A is a plan view, and FIG. 3B is the equivalent circuit diagram.
In FIGS. 3A, 3B regions surrounded by dotted lines indicate gate wiring 14 and gate terminal portions 15; regions shown as diagonal lines inside and surrounded by single dot chain lines indicate first metal wiring layer 30; and regions surrounded by bold lines indicate second metal wiring layer 50; looking from above the substrate gate wiring 14 and gate terminal portions 15 are visible through the second metal wiring layer 50 and the first metal wiring layer 30. Further, the small rectangular boxes in the diagram are the contacts 31, connecting the first metal wiring layer 30 and the substrate, and the small circles in the diagram are the through holes 51, connecting the second metal wiring layer 50 and the substrate. In the diagram only representative examples of the above items are annotated with reference labels.
This gate array, as shown in FIG. 3B, is a two input selector circuit, in which input signals applied to input terminal a, b, are selected, according to a selection signal applied to a control terminal s, and output from output terminal y.
As is seen in FIG. 3A, this is an array of 4 units of the unit cells 10 of FIG. 2A arranged in parallel. The unit cell 101 on the left edge of the figure uses inverters Ia, Ib, to invert input signals applied to input terminals a and b, and the second unit cell 102 uses the output signal from the inverters Ia, Ib as ON/OFF for transfer gates TGa, TGb. In the fourth unit cell 104 the inverter Is is used to invert the selection signal applied to control terminal s, and the inverter Iy is used to invert the signal output from transfer gate TGa or TGb in the ON condition and output to output terminal y.
The third unit cell 103 uses the first metal wiring layer 30 as the vertical direction wiring region, and the transistor gate wiring 14a, 14b in this unit cell 103 is not used. Further, in this gate array, in order to undertake wiring for the lateral direction of nodes N1, N2 and N3, the second metal wiring layer 50 is used.
In the publication of Japanese Patent Application Laid-Open (JP-A) No. H10-335613 is disclosed a semiconductor integrated circuit in which the source/drain regions of a transistor are given reduced resistance by being salicided, and these areas then used in place of first aluminum wiring in the wiring within the cell.
However, the above gate array uses the first metal wiring layer 30 at the top side of the third, unused, unit cell 103 as a vertical wiring region. Because of this three lines lateral wiring are in the second metal wiring layer 50, and the wiring efficiency is decreased, and, depending on the scale of the circuit, a further third or fourth metal wiring layer becomes necessary, making the manufacturing process more complicated.
That is, in an actual gate array, a circuit block, configured from a basic logical circuit of a number of unit cells 10 as in the example of a selector in FIGS. 3A, 3B, is referred to as a “cell” and plural cells are configured on a semiconductor substrate in the vertical and lateral directions. The wiring between the unit cells 10 within a cell is done individually by a designer manually, and recorded within the library of an automatic wiring tool. The wiring between cells in a gate array of a combination of plural cells is undertaken using an automatic wiring tool. The wiring paths between cells are determined according to the cell configurations recorded in the automatic wiring tool library. When undertaking the wiring between cells, when trying to directly connect wiring between cells if the second metal wiring layer 50 is already used within a cell, this portion cannot be arranged in the wiring between cells, giving the need for a further number of metal wiring layers, third and fourth etc, in some cases.